The present invention is related to integrated circuit structure and processing technology and, more particularly, to antifuses in integrated circuits and their manufacture.
Antifuses are found in a growing number of integrated circuits, most of which are field programmable gate arrays (FPGAs). As the name implies, antifuses have a very high resistance (to form essentially an open circuit) in the unprogrammed ("off") state, and a very low resistance (to form essentially a closed circuit) in the programmed ("on") state. In these integrated circuits antifuses are placed at the intersections of interconnection lines which lead to different elements of the integrated circuit. By programming selected antifuses, the interconnections between the various elements of the integrated circuit are formed to define the function of the device.
In a typically antifuse structure a programming layer is sandwiched between two metal interconnection lines. Depending upon the material of each metal interconnection layer and the programming layer, amorphous silicon commonly, a layer of barrier metal, such as TiW (titanium-tungsten), may be added between the programming layer and each metal interconnection layer. Barrier metal layers function to block the undesired interdiffusion of a programming layer, such as amorphous silicon, and a metal layer, such as aluminum alloy. Barrier metal layers are typically refractory metals, their intermetallics, alloys, silicides, nitrides and combinations thereof.
However, various problems have been found with present antifuses. One problem is reliability. The resistance of the programmed antifuse, R.sub.ON, is sometimes unstable. With use, R.sub.ON sometimes drifts and increases to very high values which result in a device failure. For the programmed FPGA, the failure of one antifuse is disastrous since the programmed circuit is no longer realized in the integrated circuit. This problem is believed to be caused by the deposition of the programming layer into deep vias through a thick interlayer dielectric between the metal interconnection layers. This leads to severe step coverage problems created by the deep via, i.e., an uneven deposition of the programming layer in the via, especially the corners of the via.
An antifuse structure described in U.S. Pat. No. 5,100,827, which issued on Mar. 31, 1992 to S. A. Lytle, attempts to solve this problem. The described antifuse partially addresses some of the problems of poor step coverage. Nonetheless, the antifuse structure still retains some of the disadvantages discussed above, i.e., the sharp, albeit shallower, corners in the programming and the metal interconnection layer above.
Moreover, the described antifuse structure fails to account for the parasitic capacitances of the unprogrammed antifuse. Such a failure results in the poor performance of an integrated circuit having a large number of antifuses. In present FPGAs the number of antifuses range from tens to hundreds of thousands of antifuses.
The present invention solves or substantially mitigates both problems of reliability and performance.